Data synchronizer

ABSTRACT

A data processing system in which a plurality of data channels control the simultaneous exchange of data between many input/output devices, and a common shared storage. The channels automatically extract control instructions from storage and interpret them to independently carry out data transfers. Each data channel is initialized by the central processing unit (CPU) which causes a control word to be transferred from storage to the data channel where it is stored. The data channel utilizes the control word to start an input/output operation. The input/output operation is continued automatically by the channel which has means for retrieving subsequent control words from storage independent of the CPU. Data transfers between a data channel and the storage over a common storage bus are performed by a &#39;&#39;&#39;&#39;cycle stealing&#39;&#39;&#39;&#39; capability wherein execution of the CPU program may be delayed for one storage cycle, which cycle is utilized by the channel to store a word of data in the storage. Competing requests among data channels and the CPU are resolved by a priority circuit which grants storage access to the highest priority channel demanding access. The CPU is given the lowest priority. Since the channels direct the flow of information between I/O devices and main storage, they relieve the CPU of the task of communicating directly with the devices and permit data processing to proceed concurrently with I/O operations.

United States Patent Christiansen et a1.

1 May 21, 1974 1 1 DATA SYNCHRONIZER [75] Inventors: Carl L.Christiansen; Lawrence E.

Kanter, both of Poughkeepsie; George R. Monroe, Wappingers Falls. all ofNY.

[73] Assignee: International Business Machines Corporation, New York.NY.

[22] Filed: Dec. 26. 1957 [21] Appl. No: 705.447

[52] 0.8. CI. 340/1725 [51] Int. Cl. 60619/18 [58] Field of Search235/61 PB. 61 MS, 157. 235/165, 166. 167

[56] References Cited UNITED STATES PATENTS 3.029.414 4/1962 Schrimpl340/1725 3.142.043 7/1964 Schrimpf 340/1725 3.231.865 1/1966 Wilenitz340/1725 3.234.517 2/1966 Herold et a1 340/1725 3.283.308 11/1966 Kleinet a1. 340/1725 3.334.333 8/1967 Gunderson et a1. 2.604.262 7/1952Phelps et all. 2.636.672 4/1953 Hamilton et a1. 340/1725 X 2.679.6385/1954 Bensky et a1. 340/1725 2.767.908 10/1956 Thomas 340/17252.796.218 6/1957 Toolill et a1. 340/1725 2.805.283 9/1957 Stiles 178/22.960.683 11/1960 Gregory et a1 340/1725 FOREIGN PATENTS 0R APPLICATIONS1.099.467 3/1955 France 340/1725 749.836 6/1956 Great Britain 340/1725OTHER PU BLlCATlONS E.R.A. 24-Digit Parallel Computer with Magnetic DrumMemory (PX29136)." Eng. Research Assoc.

Inc. St. Paul. Minn.. 1949. pp. 4. 5. 7-22. 27-36.

Primary liraminerRaulfe B. Zache Attorney. Agent. or Firm-Hanifin &Jancin ABSTRACT A data processing system in which a plurality of datachannels control the simultaneous exchange of data between manyinput/output devices. and a common shared storage. The channelsautomatically extract control instructions from storage and interpretthem to independently carry out data transfers.

Each data channel is initialized by the central processing unit (CPU)which causes a control word to be transferred from storage to the datachannel where it is stored. The data channel utilizes the control wordto start an input/output operation. The input/output operation iscontinued automatically by the channel which has means for retrievingsubsequent control words from storage independent of the CPU. Datatransfers between a data channel and the storage over a common storagebus are performed by a cycle stealing" capability wherein execution ofthe CPU program may be delayed for one storage cycle. which cycle isutilized by the channel to store a word of data in the storage.Competing requests among data channels and the CPU are resolved by apriority circuit which grants storage access to the highest prioritychannel demanding access. The CPU is given the lowest priority.

Since the channels direct the flow of information between [/0 devicesand main storage, they relieve the CPU of the task of communicatingdirectly with the devices and permit data processing to proceedconcurrently with 1/0 operations.

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1. A data processing system Operable by main instructions comprising, incombination, a storage device for providing a series of said maininstructions and control instructions, a plurality of input-outputdevices independently operable in response to said control instructions,and multi-channel apparatus including a control device for each of saidchannels in tandem relationship with said storage device and saidinputoutput devices, each of said channels having means to store aplurality of control instructions to be executed consecutivelyconcerning input-output operation, and means for serially moving saidcontrol instructions through said channels upon execution of any oneoperation of said input-output device.
 2. A data processing systemcomprising, in combination, a primary calculator, a plurality of controldevices, each including secondary calculating apparatus units for theinterpretation of main and control instructions, a shared storage deviceproviding a common information source of data and data handling commandsbetween said plurality of control devices and said primary calculatorand the means for communicating said data and data handling commands,and means actuated in response to stimuli from said primary calculatorto said storage device to provide initial main instructions to saidcontrol devices concerning the type of operation to be performed and thelocation in the shared storage device from which subsequent controlinstructions are extracted automatically by the control devices inresponse to operation of said secondary calculating apparatus.
 3. A dataprocessing system comprising, in combination, a device for seriallyproviding address manifestations, an addressable storage device for thestorage and transmission of data serially by word in response to saidaddress manifestations, a plurality of input-output devices forreceiving and transmitting said data, a plurality of control deviceseach independently operable in accordance with a separate programdirectly coupling said input-output devices and said storage device andeach adaptable to store and to receive address manifestations and totransmit data, from and to corresponding locations of said storagedevice in a synchronous manner and to transmit information from and tosaid input-output devices in an asynchronous manner said control devicesadapted to distribute signals representative of words of data seriallyto and from said storage device and adapted to transmit data signals inparallel, as among said input-output devices, to and from saidinput-output devices.
 4. In a data handling system, apparatus comprisinga plurality of selectively operable auxiliary storage devices adapted toreceive and store information units in response to read and writesignals, a shared storage device adapted to receive and storeinformation units in response to read-in and read-out signals, andbilateral data transmission devices coupling said auxiliary storagedevices and said shared storage device and operable in response topredetermined individual programs of control words for providing readand write signals serially to said shared storage device and forproviding said read and write signals to said selectively operableauxiliary storage devices according to said predetermined programs. 5.In a data processing unit in combination with a primary storage devicehaving individual information storage locations for receiving andtransmitting information in response to read and write signals and aplurality of secondary storage devices individually operable to receiveand transmit information in response to said read and write signals,data handling apparatus comprising at least two information transportingchannels, each channel having execution means for controlling thepassage of information between said primary storage device and saidsecondary storage devices by providing read and write signals thereto inresponse to a predetermined program stored therein, and means responsiveto said execution means and said reAd and write signals for arrangingand transmitting information in sequential order to said primary storagedevice so that said information is delivered to destinations determinedby said programs in said data handling apparatus.
 6. In a dataprocessing system including a shared storage device, a plurality ofinput-output devices, and means for controlling the passage ofinformation in a plurality of information channels therebetween, adevice for establishing priority among said channels comprising aplurality of bistable devices, one for each pair of said channels, meanscombining indications of the state of said bistable devices, meanscontrolling the state of said bistable devices in response to passage ofinformation through said channels, and means operable in response tocombined indications of said bistable devices for establishing priorityamong said channels.
 7. A data processing system adapted to execute aload channel operation in response to an instruction having anoperations part and an address part comprising a storage device, aninstruction register including means for interpreting instructions anddirecting corresponding operations, means for storing a program ofinstructions in said storage device at addresses selectable in apredetermined manner and for reading said stored instructions, aplurality of input-output devices selectable by instruction signals forstoring and transmitting data, multi-channel control apparatus adaptedto buffer information between said input-output devices and said storagedevice including operations, address and location registers respectivelyin each channel and means furnishing signals indicative of said storedinformation therein, means selecting said input-output devices and saidchannels of said control apparatus, means reading and transferring saidload channel instruction to said instruction register, means operable inresponse to said instruction register for entering the address part ofsaid load channel instruction plus a predetermined value in saidlocation register of a selected channel and for entering the informationfrom the location specified by said address contained in said loadchannel instruction in said operations and address registers in saidselected channel.
 8. A data processing system adapted to execute aninput-output control operation in response to an instruction having anoperations part, a count, and an address, said system comprising astorage device, an instruction register including means for interpretinginstructions and directing corresponding operations, means for storing aprogram of instructions in said storage device at addresses selectablein a predetermined manner and for reading said stored instructions, aplurality of input-output devices selectable by instruction signals forstoring and transmitting data, multi-channel control apparatus adaptedto buffer information between said input-output devices and said storagedevice including means storing operation manifestations, said count, andsaid addresses of locations in said storage device in each channel andfor furnishing signals indicative of said stored information, meansselecting said input-output devices and said channels of said controlapparatus, means reading and transferring an input-output controlinstruction from said storage device to a selected channel of saidcontrol apparatus, means operable in response to operationmanifestations in said operation manifestation means to program thetransfer of data in said channel, means operable in response to saidcount stored in said count storing means to control the quantity ofdata, and means operable in response to said addresses stored in saidaddress storing means to select the data locations in said storagedevice.
 9. In a data processing system adapted to execute a load channeloperation in response to an instruction having an operations part and anaddress, said system comprising a storage device and an instructionregister including means for interpReting instructions and directingcorresponding operation, means for storing a program of instructions insaid storage device at addresses selectable in a predetermined mannerand for reading said stored instructions, a plurality of input-outputdevices selectable by instruction signals for storing and transmittingdata, multi-channel control apparatus adapted to buffer informationbetween said input-output devices and said storage device includingmeans storing operation manifestations and addresses of locations insaid storage device in each channel and for furnishing signalsindicative of said stored information, means selecting said input-outputdevices and said channels of said control apparatus, means reading andtransferring a load channel instruction from said storage device to saidinstruction register, means transferring a control instruction at theaddress specified by said load channel instruction to the selectedchannel of said control apparatus, means under control of said operationmanifestations storing means, operable in response to operationmanifestations in said control instruction to program the transfer ofdata in said channel, means under control of said storing addresses oflocations, operable in response to said address in said controlinstruction to select data locations in said storage device, and meansdelaying the execution of a second of said load channel instructionswhen provided until the operation specified by said control instructionis complete.
 10. A data processing system comprising a storage device,an instruction register including means for interpreting instructionsand directing corresponding operations, means for storing a program ofinstructions in said storage device at addresses selectable in apredetermined manner and for reading out said stored instructions, aplurality of input-output devices selectable by instruction signals forstoring and transmitting data, multi-channel control apparatus adaptedto buffer information and to transfer said information between saidinput-output devices and said storage device and adapted to execute acontrol instruction having an operation part, a count, and an addressincluding means storing manifestations of said operation, said count,and said addresses in each channel and for furnishing signals indicativeof said stored control information, means selecting said input-outputdevices and said channels of said control apparatus, means reading andtransferring said control instruction from said storage device to aselected channel of said control apparatus, and execution means for eachchannel operable in response to manifestations of said operation part insaid operation storing means to control the transfer of data in saidchannel, operable in response to manifestations of said count to controlthe quantity of data transferred, and means operable in response tomanifestations of said address in said address storing means to selectthe data locations in said storage device.
 11. A data processing systemadapted to execute a synchronous load channel operation in response toan instruction having an operations part and an address part comprisinga storage device, an instruction register including means forinterpreting instructions and directing corresponding operations, meansfor storing a program of instructions in said storage device ataddresses selectable in a predetermined manner and for reading out saidstored instructions, a plurality of input-output devices selectable byinstruction signals for storing and transmitting data, multi-channelcontrol apparatus adapted to buffer information between saidinput-output devices and said storage device and controlled by bufferinstructions having operations and address parts stored in operationsand, address registers respectively in each channel, means furnishingsignals indicative of said stored information therein and ready signalswhen an operation is complete, means selecting said input-output devicesand said channels of said control appaRatus, means reading out andtransferring said synchronous load channel instruction to saidinstruction register, and synchronizing means operable in response tosaid instruction register and said ready signal from said selectedchannel for entering the buffer instructions from said address in saidstorage device into said operations and address registers in saidselected channel.
 12. A data processing system comprising, incombination, an addressable storage device, a primary computer havingaccess to said storage device for instructions and data, a plurality ofinput-output devices, a plurality of secondary stored program computersand data transmission devices for receiving and transferring data fromand to said input-output devices having access to said storage devicefor receiving instructions and data and for storing data from saidinput-otuput devices in accordance with said stored programs and meansfor establishing priority in response to demands for access to saidstorage device among said primary computer and said plurality ofsecondary computers, said priority means favoring previous demands andall demands being satisfied in a predetermined period of time.
 13. Adata processing system comprising, in combination, a computer, anaddressable storage device storing data, channel instructions andfurther instructions including select and control instructions, aplurality of input-output devices, a plurality of control devices havingchannels coupling said input-output devices to said addressable storagedevice, means for interpreting said select instructions to render onechannel operative to select a chosen input-output device, meansinterpreting said channel instructions to obtain a control instruction,means controlled by said control instruction for controlling thetransfer of data via said selected channel, means controlled by saidchannel instruction for storing in said selected channel themanifestation of the address of a next control instruction located insaid storage means, and means rendered operative upon completion of saidtransfer of data to render said manifestation of the addresses of a nextcontrol instruction effective to select and render operative said nextcontrol instruction.
 14. A device as in claim 13, and means forestablishing priority of access to said storage device between saidcomputer and said channels, and means controlled by the selected channeloperation to grant priority of access to said channel instead of to saidcomputer.
 15. A device as in claim 13, and including means forestablishing priority of access to said storage device, among saidchannels, means conditioned by operation of a chosen channel, and meanscontrolled by said conditioned means rendering said priority meansoperative to grant access to said chosen channel, in preference toanother channel.
 16. In combination, a central processing unitcontrolled by instruction manifestations and operable upon datamanifestations, addressable storage means storing manifestations ofdata, of instructions and of commands, a plurality of input-outputdevices for receiving and supplying manifestations of data, a pluralityof channels for controlling the flow of data manifestations between saidstorage means and said input-output devices and including means forstoring operation control manifestations, and address manifestations ofone kind and of another kind, said commands including operation controlmanifestations and address manifestations designating addresses of datastorage locations in said storage means, and said instructionmanifestations including address manifestations designating addresses ofcommands, means controlled by said central processing unit forextracting a manifestation of instruction from said storage means, forselecting a channel and an input-output device, means controlled by saidcentral processing unit for extracting a manifestation of an instructionfor initiating operation of said chosen channel, means controlled by aNaddress portion of said last named manifestation for storingmanifestations in accordance with said address portion in said addressmanifestation storing means of one kind, and for selecting a command atthe designated address in said addressable storage means and relayingsaid command to said operation control manifestation storage means, andto said address manifestation storage means of said other kind wherebyoperation of said selected channel is controlled by said operationmanifestation storage means to transfer data to or from said selectedinput-output unit, and from or to said data address respectively, theaddresses of data in said storage means being indicated by said addressmanifestations of said other kind, and means controlled by said addressmanifestations of said one kind for selecting a command in said storagemeans, to control further data transfer.
 17. A device, as in claim 16,and including means in each channel for storing data quantitymanifestations, and said commands including a data quantitymanifestation, and means controlled by the address portion of said lastnamed manifestation, relaying said data quantity manifestation to saiddata quantity manifestation storing means, means operating upon saiddata quantity manifestation to keep track of the amount of datatransferred by altering said manifestation to different statuses andmeans rendered operative by a certain status to render said means,controlled by said address manifestation of said one kind, effective forselecting another command.
 18. A device, as in claim 16, and includingmeans establishing a priority of access to said storage means betweensaid central processing unit and said channels, and means controllingsaid priority access means to give priority of access to a channel, uponsimultaneous demands for access by said central processing unit and saidchannels.
 19. A device, as in claim 16, and including means establishingpriority of access to said storage means between two channels, meanscontrolled by operation of said channels to indicate a present state ofoperation or of non-operation, respectively, of said two channels, andmeans controlled by said last indicating means for rendering saidpriority means effective to grant access to said channel indicating apresent state of operation.
 20. A device, as in claim 16, and includingmeans establishing priority of access to said storage means among aplurality of channels simultaneously requesting access, meansconditioned selectively by operation of one channel to establish a claimof priority, and means controlled by first and second, associated unitsin said one channel, for controlling said conditioned means wherebypriority among said channels simultaneously requesting access in givento said second associated unit in said one channel, if said firstassociated unit was immediately previously operative, but no longerrequesting access to said storage means.
 21. In combination, a computer,a plurality of input-output devices and a shared addressable storageunit, said unit storing manifestations of data, instructions andcommands, each of said instructions including an operation part and anaddress part and each of said commands including a word count part, anoperation designating part and an address part, a plurality of channelsconnecting said input-output devices and said shared storage unit andeach including a data register for receiving data manifestations fromsaid input-output devices to be relayed to said storage unit or datamanifestations from said storage unit to be relayed to said input-outputunits, a location register in each said channel for storingmanifestations of said instruction address part, a word counter in eachsaid channel for storing manifestations of said command word count part,an address counter in each said channel for storing manifestation ofsaid command address part, an operation register in each channel forstoring said command operations part, means controlled by aN instructionfor selecting a channel and selecting an input-output device, meanscontrolled by an address part of an instruction for storing said addresspart in said location counter, and for selecting a command in saidstorage unit, means controlled by said last named instruction operationpart for transferring said word count part of said selected command tosaid word address counter, said word address part of said selectedcommand to said word address counter and said operation part of saidselected command to said operation register, means for stepping saidword counter down and said address counter up, said operation partstored in said operation register, controlling the flow of data to saiddata register, said flow controlling said word counter, said wordaddress counter designating the storage location of data in said storageunit, and means controlled by said word counter, upon termination ofsaid data transfer, to request access to said storage unit, said addressstored in said location register selecting the address of the nextcommand stored in said storage unit.
 22. A device, as in claim 21, andincluding means demanding access to said storage means by said computerand said selected channel and means recognizing both said demands foraccess, said means granting priority to said channel demand uponsimultaneous demand by said computer and said channel.
 23. A devive, asin claim 21, and including means recognizing demands for access by aplurality of channels, and means granting priority to said firstselected channel, upon a demand emanating from said channel and anotherchannel.
 24. Apparatus for providing service in turn to the individualones of a plurality of devices arranged into a number of groups, eachdevice operable to request service, means establishing service to anindividual device, including: means for recognizing which devicesrequest service and which ones have previously been provided service;means for providing priority of service, as among groups of said devicesrequesting simultaneous service, to the group having the device beingpresently serviced; and means for providing priority of service, asamong devices requesting service in a group, to the device previouslyserviced.
 25. Apparatus for indicating priority of service among aplurality of input line groups carrying signals representative ofservice requests, including: a number of bi-stable flip-flops, eachsettable to a selected one of a first and a second state, and eachassociated with a different group of said input lines; means operativeto permit setting to said first state of selected ones of saidflip-flops by service signals on any input line in selected ones of saidgroups; means operative to permit setting to said second state ofselected ones of said flip-flops by service signals on any input line inselected ones of said groups associated with selected others of saidflip-flops; means operative to maintain the state of any of saidflip-flops when service signals attempt to set said flip-flop to saidfirst and second states substantially simultaneously; gating meansassociated with each flip-flop responsive to the state of a number ofothers of said flip-flops; and group-priority indicating output meansassociated with each flip-flop responsive to said associated gatingmeans and operative by the first state of said associated flip-flop. 26.A device as in claim 25 wherein said gating means is responsive to thefirst state of said associated flip-flops and to the second state ofsaid other flip-flops.
 27. A device as in claim 25 wherein each of saidgroup-priority indicating output means is associated with: a number ofline-priority indicating output means corresponding to the number ofinput lines comprising a group, a selected one of said line-prioritymeans corresponding to the input line carrying a service request beingoperable when said associated group-priority means is operative.
 28. Inan electronic data processing apparatus, the coMbination comprising aplurality of data utilization devices, each of said devices having aseparate demand line to indicate when active the readiness of saiddevice to manipulate data, a control means comprising means foraddressing a data storage location for data to be manipulated, anaddressable data storage means adapted to have data read therefrom orwritten thereinto in accordance with addresses derived fon said controlmeans, and a traffic control circuit separately connected to each demandline of said utilization devices and said control means to substantiallyimmediately scan all demand lines connected thereto, bypassing alldemand lines which are inactive without response therefrom, until anactive demand line is sensed and passing separate control signals tosaid control means for each active demand line sensed.
 29. Incombination, a plurality of data manipulating devices, a multiple stagetraffic control circuit, a data processor, means including said trafficcontrol circuit repetitively scanning all of said devices and connectingeach of said data manipulating devices requiring a data manipulation insequence to said data processor to perform a single data manipulation,an error signal producing circuit, and electronic switching means undercontrol of said error signal producing circuit connected to said trafficcontrol circuit to interrupt said traffic control circuit in at leastone stage upon the occurrence of an error in a data manipulation.
 30. Incombination, a plurality of data manipulating devices, a multiple stagetraffic control circuit, a data processor connected to one stage of saidtraffic control circuit to be activated thereby, means including saidtraffic control circuit repetitively scanning all of said devices andconnecting each of said data manipulating devices requiring a datamanipulation in sequence to said data processor to perform a single datamanipulation, an error signal producing circuit, an electronic switchingmeans under control of said error signal producing circuit connected tosaid traffic control circuit to interrupt said traffic control circuitin at least one stage upon the occurrence of an error in a datamanipulation.
 31. A data manipulating apparatus comprising data supplymeans having a plurality of data items therein each arranged as aplurality of data words, and an end-of-item indicator separating therespective items, a memory unit having a plurality of separatelyaddressable storage locations to which all of said data is to betransferred, a memory address selector, control means adapted to storeaddress data defining an address in said memory unit, means includingsaid control means activated by each incoming data word to transferdirectly the data word unmodified to an address location specified bysaid address data from said control means, means including said controlmeans modifying the address defining data each time said address data isused, an end-of-item indicator sensing means, and means including saidend-of-item sensing means connected to effect modification of theaddress data in said control means.
 32. A data manipulating apparatuscomprising data supply means having a plurality of data items thereineach arranged as a plurality of data words, and an end-of-item indicatorseparating the respective items, a memory unit having a plurality ofseparately addressable storage locations to which all of said data is tobe transferred, a memory address selector, control means adapted tostore address data defining an address in said memory unit, meansincluding said control means activated by each incoming data word totransfer directly the data word unmodified to an address locationspecified by said address data from said control means, means includingsaid control means modifying the address defining data each time saidaddress data is used, an end-of-item indicator sensing means, and meansincluding said end-of-item sensing means connected to effectmodification of the address data in said Control means, said last-namedmeans comprising memory output sensing means connected to said memoryaddress selector and to said control means.
 33. A data manipulatingapparatus comprising data supply means having a plurality of data itemstherein each arranged as a plurality of data words, and an end-of-itemindicator separating the respective items, a memory unit having aplurality of separately addressable storage locations to which all ofsaid data is to be transferred, a memory address selector, control meansadapted to store address data defining an address in said memory unit,means including said control means activated by each incoming data wordto transfer directly the data word unmodified to an address locationspecified by said address data from said control means, means includingsaid control means modifying the address defining data each time saidaddress data is used, an end-of-item indicator sensing means, and meansincluding said end-of-item sensing means connected to effectmodification of the address data in said control means, said last-namedmeans comprising memory output sensing means connected to said memoryaddress selector and to said control means, said control means modifyingthe data received from said memory output sensing means.
 34. Apparatusfor arranging a plurality of data words in an addressable main memorycomprising a control memory having a plurality of addressable storagepositions, a control memory address selector, means connected to saidcontrol memory address selector to set a predetermined address thereinindicative of an incoming word, a main memory address selector, meansincluding said control memory address selector reading an address forsaid main memory from said predetermined address in said control memoryinto said main memory address selector to select a location in said mainmemory for said incoming word, and means connected to said controlmemory to modify the main memory address from said predetermined addressin said control memory and reinsert said modified main memory address atsaid predetermined address in said control memory.
 35. Apparatus fortransferring a plurality of data words relative to an addressable mainmemory comprising a control memory having a plurality of addressablestorage positions, a control memory address selector, means connected tosaid control memory address selector to set a predetermined addresstherein indicative of the need for a data word to be transferred, a mainmemory address selector, means including said control memory addressselector reading an address for said main memory from said controlmemory into said main memory address selector to select a location forsaid data word which is to be transferred, and means connected to saidcontrol memory to modify the main memory address from said predeterminedaddress in said control memory and reinsert said modified main memoryaddress at said predetermined address in said control memory. 36.Apparatus for transferring a plurality of data words relative to anaddressable main memory comprising a control memory having a pluralityof addressable storage positions, a control memory address selector,means connected to said control memory address selector to set apredetermined address therein indicative of the need of a word to betransferred, a main memory address selector, means including saidcontrol memory address selector reading an address for said main memoryfrom said control memory into said main memory address selector toselect a location for said word which is to be transferred, meansconnected to said control memory to modify the main memory address fromsaid control memory and reinsert said modified main memory address atsaid predetermined address in said control memory, and means connectedto said control memory to effect a transfer from said main memory ofsubstitute control data for insertion in said predetermined address insaid control memory.
 37. In a data processing apparatus, the combinationcomprisinG a main memory, said memory being adapted to store data wordseach at a separately addressable location, a main memory addressselector for selecting the address for each data word in said mainmemory, a control memory having a plurality of addressable storagelocations, said control memory being adapted to store control data forsaid main memory, a control memory address selector, a data transfercircuit, indicating means connected to said last-named circuit toindicate said transfer circuit is conditioned to transfer a data word,means including said indicating means setting an address in said controlmemory address selector, control memory activating means connected tosaid control memory to read control data therefrom at a selected addresslocation into said main memory address selector, means including saidmain memory address selector effecting a direct transfer of data withoutmodification between said transfer circuit and said main memory, andmeans connected to said control memory to modify the control data readinto said main memory address selector.
 38. Apparatus for arranging aplurality of data words in an addressable main memory comprising acontrol memory having addressable storage locations, a control memoryaddress selector, means connected to said control memory addressselector to set a first predetermined address therein indicative of aword to be transferred, a main memory address selector, means includingsaid control memory address selector reading an address from saidcontrol memory into said main memory address selector to select alocation in said main memory for said incoming word, means connected tosaid control memory to modify the main memory address from said controlmemory and reinsert said modified main memory address at saidpredetermined address, word sensing means connected to said main memoryto sense the contents of each word transferred, said word sensing meansbeing connected to said control memory address selector to set a secondpredetermined address therein so that a special address in said mainmemory will be selected and data at said special address will beinserted into said first predetermined address in said control memory.39. In a data processing apparatus, the combination comprising a mainmemory, said memory being adapted to store data words at separatelyaddressable storage locations, a main memory address selector forselecting the address for each data word in said main memory, a controlmemory having a plurality of addressable storage locations, said controlmemory being adapted to store control data for said main memory, acontrol memory address selector, a data transfer circuit, indicatingmeans connected to said last-named circuit to indicate said transfercircuit is conditioned to transfer a data word, means including saidindicating means setting a first address in said control memory addressselector, control memory activating means connected to said controlmemory to read control data therefrom into said main memory addressselector, means including said main memory address selector effecting atransfer of data between said transfer circuit and said main memory,means connected to aid control memory to modify the control data readinto said main memory address selector, selective data sensing meansconnected to said data transfer circuit, means connecting said datasensing means to said control memory address selector to set a secondaddress therein, and means including said data sensing means effecting achange of the data in said control memory at said first address. 40.Apparatus for arranging a plurality of data words in an addressable mainmemory comprising a control memory having a plurality of addressablestorage locations, a control memory address selector, means connected tosaid control memory address selector to set a predetermined addresstherein indicative of a word to be transferred, a main memory addressselector, means including said control memory address selector reading afirst address froM said control memory into said main memory addressselector to select a location for said incoming word, and meansconnected to said control memory to modify by unity the main memoryaddress from said control memory and reinsert said modified main memoryaddress at said predetermined address in said control memory.
 41. In adata processing apparatus, the combination comprising a plurality ofdata utilization devices, each of said devices being adapted to receiveand transmit data, a programmed data processor, a traffic controlcircuit, demand indicating lines connected from each of said utilizationdevices to said traffic control circuit, electronic switching meansconnected to said traffic control circuit to scan substantiallyimmediately all of the demand lines until an active demand line issensed. said switching means being adapted to lock directly onto onlythose demand lines in a selected sequence which are active and bypassingwithout response therefrom those demand lines which are inactive, datastorage means, and control means comprising data selecting meansconnected to be controlled by each utilization device whose demand lineis active, said control means being connected to effect a data transferwith respect to said data storage means in accordance with the device indemand.
 42. In combination, in a data processing apparatus, a first datamanipulation traffic control adapted to scan a plurality of operationdemand lines and initiate a control signal and thereby a datamanipulation only with respect to each active demand line which iscalling for operation, a second data manipulation traffic controladapted to scan a plurality of operation active demand lines andinitiate a control signal and thereby a data manipulation only withrespect to each active demand line which is calling for operation, adata processor connector to receive control signals from said first andsecond traffic controls to initiate a control action in said dataprocessor related to a selection made by said second traffic control.43. In combination, in a data processing apparatus, a first datamanipulation traffic control adapted to scan a plurality of operationdemand lines and initiate a control signal and thereby a datamanipulation only with respect to each active demand line which iscalling for operation, a second data manipulation traffic controladapted to scan a plurality of operation demand lines and initiate acontrol signal and thereby a data manipulation only with respect to eachactive demand line which is calling for operation, a data processorconnector to receive control signals from said first and second trafficcontrols to initiate a control action in said data processor related toa selection made by said second traffic control, and means to step saidsecond traffic control after a predetermined operation of said dataprocessor when under the control of said second traffic control.
 44. Incombination, in a data processing apparatus, a first data manipulationtraffic control adapted to scan a plurality of operation demand linesand initiate a control signal and thereby a data manipulation only withrespect to each active demand line which is calling for operation, asecond data manipulation traffic control adapted to sense a plurality ofoperation demand lines and initiate a control signal and thereby a datamanipulation only with respect to each active demand line which iscalling for operation, a data processor connected to receive transfercontrol signals from said first traffic control and data manipulationprogram orders from said second traffic control to initiate a controlaction in said data processor related to a selection made by said secondtraffic control.
 45. In combination with a data processor, a pluralityof peripheral data handling devices said devices each being adapted tohave an output operational demand signal which is active when saiddevice is ready to operate, an operational traffic control having aplurality of coNtrol stations, each station of which is connected to oneeach of said peripheral devices to sense only the active operationaldemand signals produced by said devices and to bypass without responsetherefrom those devices having no operational demand signal, a trafficcontrol signal source comprising an electronic switching means connectedto said traffic control to step said traffic control from one activedemand signal to the next so that each device receives at least oneoperational control impulse for a predetermined data manipulation afterwhich the traffic control steps substantially immediately to the nextactive demand signal, and a control circuit connected to be controlledby the output from said traffic control.
 46. In combination with a dataprocessor, a plurality of peripheral data handling devices each of saiddevices having an input buffer and an output buffer, and the buffers ofsaid devices each being adapted to have an output operational demandsignal which is active when the associated buffer is ready to operate,an operational traffic control having a plurality of control stationseach independently connected to one each of said buffers to sense activeoperational demand signals produced by said buffers and to bypasswithout response therefrom any buffer not having an active operationaldemand signal, a traffic control signal source connected to said trafficcontrol to step said traffic control from one active operational demandsignal to the next so that each buffer receives at least one operationalcontrol impulse for a predetermined data manipulation after which thetraffic control steps substantially immediately to the next activedemand line, and a control circuit connected to be controlled by theoutput from said traffic control.
 47. In a data processing apparatus,the combination comprising a plurality of data utilization devices, eachof said devices being adapted to receive and transmit data, a programmeddata processor, a traffic control circuit, demand indicating linesconnected from each of said utilization devices to said traffic controlcircuit, electronic switching means connected to said traffic controlcircuit to scan substantially immediately all of the demand lines,bypassing without response therefrom the inactive demand lines, until anactive demand line is sensed, data storage means, control meanscomprising data selecting means connected to be controlled by eachutilization device whose demand line is active, said control means beingconnected to effect a data transfer with respect to said data storagemeans in accordance with the device in demand, and clock means producinga traffic control signal connected to said signal means to switch saidtraffic control circuit from one active demand indicating line to thenext active demand indicating line.
 48. An on-line data processingsystem for processing call requests from keysets and the like comprisinga central processing portion, said central processing portion includinga computer means and means for receiving said call requests, a pluralityof peripheral units, each of said peripheral units including informationstorage means and control register means, said central processingportion also including means responsive to a received call request fordirecting to said control register means data for controlling thetransfer of information between said information storage means and saidcentral processing portion, and transfer means for each of saidperipheral units, said transfer means being controlled by said controldata to carry out the transfer of information between the correspondingone of said peripheral units and said central processing portion.
 49. Adata processing system as set forth in claim 48, including means at saidperipheral units to develop a BID signal indicating that thecorresponding peripheral unit is conditioned for a transfer ofinformation, and means at said central processing portion responsive tosaid BID siGnal for inhibiting the operation of said computer means topermit said transfer to take place.
 50. A data processing system as setforth in claim 49 further including priority selector means for enablinga predetermined one of said transfer means in accordance with apredetermined priority schedule.
 51. In an on-line data processingsystem for processing call requests comprising a central processorportion including data storage means, computer means operable upon datastored in said data storage means, and means for receiving said callrequests and for directing corresponding data signals to said datastorage means to be operated on by said computer means; a plurality ofperipheral units for storing inventory information to be processed inaccordance with said call requests each of said peripheral unitsincluding control register means, said computer means being operative inaccordance with said call requests to load instructional data in aselected one of said control register means, said peripheral unitsfurther including transfer means responsive to said control registermeans in accordance with said instructional data for identifyingparticular inventory information and for effecting a transfer thereofbetween said data storage means and said inventory storage means.
 52. Adata processing system as set forth in claim 51 wherein said transfermeans further includes synchronizing register means for temporarilystoring said identified information.
 53. In an on-line data processingsystem, a central processor portion, a plurality of periheral units eachincluding inventory storage means and control register means, saidcentral processor portion including a computer section and data storagemeans operable with said computer section, a plurality of keysets forinitiating call requests and for directing said call requests to saidcentral processor portion, means included at said central processorportion for receiving said call requests and for transmitting transferinstructional data to a selected one of said control register meanscorresponding to identifying signals contained in the call request, saidcontrol register means including means for addressing said data storagemeans and said inventory storage means and means for establishing theoperational state of said peripheral unit, and synchronizing registermeans for receiving digits of inventory information to be transferredbetween a selected peripheral unit and said data storage means.
 54. Dataprocessing system as set forth in claim 53, including signal means ateach peripheral unit for generating a BID signal when that peripheralunit is conditioned to effect a transfer of inventory information,priority selector means responsive to said BID signals so generated fordeveloping an ALLOW signal individual to one of said peripheral unitsaccording to a preset priority schedule, and means at said peripheralunits responsive to the ALLOW signal to carry out the selected datatransfer.
 55. A data processing system as set forth in claim 54,including inhibiting means at said central processor, said inhibitingmeans being responsive to a BID signal and operative thereby to preventfurther operations of said computer section until the data transfer hasbeen effected.
 56. An on-line data processing system comprising acentral processor portion and a plurality of peripheral units arrangedfor operation with said central processor portion, said centralprocessor portion including data storage means and program control meanshaving a plurality of preset programs, means for directing call requeststo said central processor portion on a random basis, said centralprocessor portion including means for receiving said call requests on aone-at-a-time basis, control register means at said peripheral unitsarranged to receive instructional data defining a particular datatransfer operatIon between the peripheral unit and said data storagemeans, said central processor portion including means responsive tosignals of a call request for transmitting to said control registermeans a particular preset program corresponding to said signals of thecall request, synchronizing register means for storing the informationto be transferred on a bit basis, means operative upon said peripheralunit being conditioned to effect a transfer of a bit of inventoryinformation for providing a BID signal, access providing meansresponsive to a BID signal for selectively providing communicationbetween one of said peripheral units and said central processor portionaccording to a predetermined priority schedule, and means included insaid control register means for addressing said data storage means uponaccess being provided to said one peripheral unit for transferring saidbit of inventory information.
 57. An on-line data processing system forprocessing call requests comprising a central processing portion and aplurality of peripheral units, said central processor portion includingdata storage means and program means for containing a plurality of setsof instructional data to be selectively transmitted to a selected one ofsaid peripheral units in response to identifying signals forming part ofeach request, each of said peripheral units including inventory storagemeans and control register means to receive said selected instructionaldata for independently controlling the transfer of inventory informationbetween said data storage means and said inventory storage means,synchronizing register means for temporarily storing said inventoryinformation to be transferred, means for indicating the conditioning ofsaid temporary storing means for the transfer of inventory information,means responsive to said indicating means for selectively providingcommunication between said one peripheral unit and said centralprocessor portion according to a predetermined priority schedule, meansincluded in said control register means for addressing said data storagemeans upon communication being provided to said one peripheral unit, andmeans for transferring said inventory information between said temporarystoring means and said data storage means as addressed by saidaddressing means.
 58. An on-line data processing system for processingcall requests including a central processor portion having input/outputstorage means and a plurality of peripheral units, each of saidperipheral units including inventory storage means and means foreffecting a transfer of inventory information between the inventorystorage means and said input/output storage means, said transfer meansincluding individual programming means for said peripheral unit; saidprogramming means including control register means having state registermeans operative for determining the operational state of said peripheralunit, inventory register means for addressing said inventory storagemeans, and processor register means for addressing said input/outputstorage means; means forming part of said central processor portion fordirecting to said control register means program instructions developedin accordance with signals contained in a received call request;synchronizing register means for effecting the transfer of data betweensaid inventory storage means and said input/output storage means, andmeans responsive to said synchronizing register means for determiningpreferential communication between a particular one of said peripheralunits and said central processor portion.
 59. A data processing systemas set forth in claim 58 further including means for modifying theinstructional data in said inventory register means and said processorregister means upon each transfer of data between said input/outputstorage means and said inventory storage means.
 60. An on-line dataprocessing systeM for processing call requests comprising means forreceiving said call requests on a random basis, a central processorportion including a data storage means and program control means, aplurality of peripheral units each having control register means andinventory storage means, said program control means having a pluralityof preset programs and operative upon the receipt of a call request totransmit a particular one of said preset programs to said controlregister means, addressing means forming part of said control registermeans for defining a block of information addresses of said inventorystorage means and for defining a block of information addresses of saiddata storage means, each of said peripheral units includingsynchronizing register means for receiving inventory information to betransferred between said data storage means and said inventory storagemeans, each of said peripheral units further including means forgenerating a signal indicative of a transfer condition therefor, andmeans responsive to said signals so generated for transferring saidinventory information on a preferential basis between a selected one ofsaid synchronizing register means and said data storage means of saidcentral processor portion.
 61. An on-line data processing systemincluding a central processor portion and a plurality of peripheralunits and means for transferring information between individual ones ofsaid peripheral units and said central processor portion, saidtransferring means including a priority selector device and circuitmeans responsive to said priority selector device for interconnectingsaid central processor portion and said peripheral units, said priorityselector device being responsive to said peripheral units being in atransfer condition and operative to provide access through said circuitmeans between a selected one of said peripheral units and said centralprocessor portion according to a predetermined priority schedule, saidperipheral units including individual programming means for controllingthe transfer of information between said particular one of saidperhipheral units and said central processor portion through saidcircuit means.
 62. A data processing system as in claim 61 wherein saidcentral processor portion and said peripheral units each include storagemeans between which information is to be transferred, said individualprogramming means each including first means for addressing said storagemeans of said central processor portion and second means for addressingsaid storage means of said peripheral unit.
 63. A data processing systemas in claim 62 wherein each of said first and second means is a workingstorage register adapted to be decremented upon each addressingoperation thereby.
 64. A data processing system as in claim 61, whereinsaid priority selector device comprises a plurality of input terminalseach coupled to one of said peripheral units to receive a BID signaltherefrom, a plurality of output terminals each corresponding to one ofsaid peripheral units an interconnecting circuit between each inputterminal and the corresponding output terminal, said interconnectingcircuits including gate means operable, in response to a higher-priorityBID signal, to inhibit the development of an output signal on its outputterminal.
 65. An on-line data processing system for inventory controlpurposes comprising a central processing portion including a computersection and an addressable data storage means, a plurality of randomlyoperative keysets for originating any of a number of call requests, aplurality of peripheral units including means for maintaining currentrecords of inventory information to be processed in response to saidradomly received call requests, said central processing portionincluding means for individually programming selected ones of saidperipheral units in accordance with a Received call request, each ofsaid peripheral units including control register means for storing saidprograms and means for temporarily storing information to be transferredto and from said central processing portion, means responsive to thestorage state of said temporary storing means for seeking access to saidcentral processing portion, means responsive to said access seekingmeans for determining preferential access for a particular peripheralunit according to a priority schedule, first means responsive to saiddetermining means for transferring inventory information between saidtemporary storing means of a preferred peripheral unit and said centralprocessor, and means for inhibiting said computer section of saidcentral processing portion during a transfer of said inventoryinformation.
 66. In an on-line data processing system comprising acentral processor portion and a plurality of peripheral units, each ofsaid plurality of peripheral units including control register means andinventory storage means for inventory statistics, a plurality ofkeysets, said central processor portion being responsive to said keysetson a random basis for transmitting predetermined program instructions tosaid control register means, said register means being operative therebyto address said inventory storage means, temporary storage means, firstmeans responsive to said control register means for transferring saidinventory statistics on a bit basis between said inventory storage meansand said temporary storage means, and second means for controlling thetransfer of said bits of said inventory statistics on a preferentialbasis between said temporary storage means of said perhipheral units andsaid central processor portion.
 67. A data processing system as claimedin claim 66, wherein said control register means includes a registerstage for indicating the number of data transfer operations to becarried out, and means responsive to said register stage for stoppingfurther transfer operations after the required number have beencompleted.
 68. In an on-line data processing system, a central processorportion including means for storing a plurality of preset programs andfor receiving a plurality of call requests on a random basis, aplurality of peripheral equipments associated with said centralprocessor portion said processor portion being operative in response toan individual call request to direct a predetermined one of said presetprograms to a particular one of said peripheral equipments, saidperipheral equipments each including control register means forreceiving said predetermined program, storage means included in each ofsaid peripheral units, said control register means further includingmeans for storing instructions representing a present address of saidstorage means, means responsive to said control register means foraddressing said storage means, and means for decrementing said storedaddress instructions upon each addressing of said storage means.
 69. Inan on-line data processing system comprising, a central processorportion including data storage means addressable on a random basis, aplurality of peripheral units associated with said central processorportion, each of said peripheral units including inventory storage meansand control register means for independently controlling the operationthereof, said control register means including means to receive fromsaid central processor portion program instructions developed inaccordance with a received call request, said control register meansincluding first means for addressing said data storage means and secondmeans for addressing said inventory storage means, means responsive tosaid control register means for transferring inventory statisticsbetween said inventory storage means and said data storage means, saidtransfer means inclUding means operative to modify said control registerfirst and second means upon a transfer being effected whereby the nextaddress of said inventory storage means of said peripheral unit isidentified and the next address of said storage means of said centralprocessor portion is identified.
 70. An on-line data processing systemcomprising a central processor portion and a plurality of peripheralunits, said central processor portion comprising computer means andrandomly accessible first storage means adapted as an input/outputdevice for said computer means, said peripheral units each including acontrol register means and a second storage means for storing inventorystatistics and the like, said central processor portion also includingmeans for developing instructional data for effecting the operation ofany one of said control register means in accordance with the specificnature of a call request, said control register means including meansfor addressing said first and said second storage means in accordancewith said instruction data, and means responsive to said controlregister means for effecting a transfer of information between saidfirst and second storage means.
 71. A data processing system as setforth in claim 70 including means for interrupting the operation of saidcomputer means concurrently with the operation of said transfereffecting means.
 72. A data processing system as set forth in claim 71,including means for controlling the operation of said transfer effectingmeans on a predetermined priority schedule.
 73. An on-line dataprocessing system comprising a central processor portion for processinginventory statistics in accordance with a received call request, saidprocessor portion including computer means having an addressableinput/output storage means, a plurality of peripheral units for storinginventory statistics to be processed by said computer means andincluding inventory storage means, control register means for each ofsaid peripheral units and adapted to be selectively instructed by saidcentral processor portion in accordance with a received call request;said control register means including first register means forestablishing the operational state of said peripheral unit, secondregister means defining one address of a group of addresses of saidinventory storage means, and third register means for defining oneaddress of a group of addresses of said input/output storage means;means controlled by said first register means in accordance with saidoperational state for effecting a transfer of inventory statistics on abit basis between consecutive corresponding addresses of said inventorystorage means and said input/output storage means; means operative tomodify the instructions contained in said second and third registermeans upon each addressing of said inventory storage means and saidinput/output storage means respectively; and means for controlling theoperation of said transfer effecting means on a preferential basisaccording to a priority schedule.
 74. A data processing system as setforth in claim 73 wherein means are included in said control registermeans for interconnecting said first, second and third registers in aregister arrangement.
 75. In a data processing system having a centralprocessor portion and a plurality of peripheral units to be providedpreferential access to said central processor portion, each of saidperipheral units including means for generating a BID signal, priorityselector means having a plurality of input terminals each assigned alower order of priority than the preceding input terminal, acorresponding plurality of output terminals, each of said inputterminals being connected to a predetermined one of said BID signalgenerating means, said selector means including logic meansinterconnecting each input terminal to a corresponding output terminal,each of said logic means including an inhibit terminal connected to theinput terminals of higher assigned priority, said output terminals beingoperative to provide communication between the corresponding one of saidperipheral units and said central processor portion.
 76. A dataprocessing system comprising a plurality of peripheral data transmittingand receiving devices, a plurality of channels each adapted to establishan operative relationship with respective ones of said peripheraldevices, a memory subsystem having a unique cell reserved for each ofsaid channels, said cell containing the indirect address of a memorybuffer area, a general purpose arithmetic subsystem for performingcomputation upon binary coded data and for receiving both arithmetic andinput/output commands from said memory subsystem, said arithmeticsubsystem including means for distinguishing an input/output command andinitiating a data exchange between a selected peripheral device and thememory buffer area associated with its channel, and means responsive toa predetermined command word for providing an operational mode providinga continuous data exchange between a selected peripheral device andmemory buffer area independent of said arithmetic subsystem.
 77. Thedata processing system defined in claim 76 comprising means forinhibiting data transfers between said peripheral devices and saidmemory subsystem during said operational mode, said means beingindependent of said airthmetic subsystem.
 78. The data processing systemdefined in claim 76 comprising means for regulating the flow of databetween said memory subsystem and said peripheral data transmitting andreceiving devices so that the devices having the highest data rates areautomatically afforded the highest priority use of said memorysubsystem.
 79. In a data processing system, the combination of: aplurality of peripheral data transmitting and receiving devices, aplurality of channels each adapted to establish an operativerelationship with respective ones of said peripheral devices, a memorysubsystem having a unique cell reserved for each of said channels, andmeans operating in conjunction with said channels and said memorysubsystem for providing an operational mode wherein one or more of saidperipheral devices may continuously exchange data with a selected memoryarea.
 80. In the data processing system defined in claim 79, means forgenerating a binary encoded code corresponding to each channel forautomatically generating the address of said reserved cell.
 81. In thedata processing system defined in claim 79, means for regulating theflow of data between said memory and said peripheral data transmittingand receiving devices so that the devices having the highest data ratesare automatically afforded the highest priority use of said memory. 82.In the data processing system defined in claim 79, a general purposearithmetic subsystem for performing computation upon binary coded dataand for receiving both arithmetic and input/output commands from saidmemory, said arithmetic subsystem including means for distinguishing aninput/output command and subsequently transferring said command to oneof said channels after which said arithmetic subsystem is free forperforming arithmetic computations and receiving subsequent commandsfrom said memory.
 83. In a computer system, a processor capable ofprocessing data in a plurality of cycles, said processor including arandomly accessible memory capable of being selectively chosen foraccess by said processor in any one or more of said cycles, saidprocessor including means operable in each cycle to provide a processorrequest signal indicating whether or not the processor requires accessto the memory during the next cycle, said processor also includingtiming means for initiating a processor cycle and for providing timingsignalS during each initiated processor cycle, at least one peripheralunit including means for providing a peripheral request signalrequesting access to said memory, said peripheral unit being capable ofrandomly accessing said memory independently of said processor to permitdata to be transferred therebetween, the period of a cycle of saidprocessor being relatively small with respect to the period betweentransfers of data by said peripheral unit, first control means coupledto said timing means and responsive to said processor and peripheralrequest signals for inhibiting generation of a new processor cycle whenboth said processor and said peripheral unit request use of the memoryfor the same period, and second control means for initiating access ofsaid memory by said peripheral unit in response to a request for samewhenever said processor is not making use of said memory.
 84. In acomputer system, a processor capable of processing data in a pluralityof cycles, said processor including a randomly accessible memory capableof being selectively chosen for access by said processor in any one ormore of said cycles, said processor including means operable in eachcycle to provide a processor request signal indicating whether or notthe processor requires access to the memory during the next cycle, saidprocessor also including timing means for initiating a processor cycleand for providing timing signals during each initiated processor cycle,at least first and second peripheral units each including means forproviding a peripheral request signal requesting access to said memory,each peripheral unit being capable of randomly accessing said memoryindependently of one another and of said processor, the period of acycle of said processor being relatively small with respect to theperiod between transfers of data by a peripheral unit, first controlmeans coupled to said timing means and responsive to said processor andperipheral request signals for inhibiting generation of a new processorcycle when said processor and at least one peripheral unit request useof the memory for the same period, second control means for giving oneperipheral unit priority over the other for access to said memory, thirdcontrol means for initiating access of said memory by a peripheral unitwhenever said processor or the other peripheral unit is not making useof same, and means cooperating with said first control means forpermitting generation of a new processor cycle after access of saidmemory by a peripheral unit.
 85. In a computer system, a processorcapable of processing data in a plurality of cycles, said processorincluding a randomly accessible memory capable of being selectivelychosen for access by said processor in any one or more of said cycles,said processor including means operable in each cycle to provide aprocessor request signal indicating whether or not the processorrequires access to the memory during the next cycle, a processor addressregister and a processor input-output register cooperating with saidmemory to permit access of a selected address in said memory inaccordance with said processor address register, at least one peripheralunit including means for providing a peripheral request signalrequesting access to said memory, said peripheral unit also including aperipheral address register and a peripheral input-output registercapable of cooperating with said memory in the same manner as saidprocessor address register and said processor input-output register, theperiod of a cycle of said processor being relatively small with respectto the period between transfers of data by said peripheral unit, meansfor gating said registers so as to permit either the processor or saidperipheral unit to access said memory independently of one another,first control means responsive to said processor and peripheral requestsignals for inhibiting genEration of a new processor cycle when bothsaid processor and said peripheral unit request use of the memory forthe same period, and second control means for initiating access of saidmemory by said peripheral unit in response to a request for samewhenever said processor is not making use of said memory.
 86. In acomputer system, a processor capable of processing data in a pluralityof cycles, said processor including a randomly accessible memory capableof being selectively chosen for access by said processor in any one ormore of said cycles, said processor including means operable in eachcycle to provide a processor request signal indicating whether or notthe processor requires access to the memory during the next cycle, saidprocessor including processor memory access indicating means forindicating when the processor is using the memory and processor memoryrequest indicating means for indicating whether the processor requestsaccess to the memory during the next processor cycle, at least oneperipheral unit including peripheral request indicating means forindicating when said peripheral unit requests access to said memory, theperiod of a cycle of said processor being relatively small with respectto the period between transfers of data by said peripheral unit, meanscoupled to said processor memory request indicating means and saidperipheral request indicating means for inhibiting generation of a newprocessor cycle when both said processor and said peripheral unitrequest access to the memory for the same period, and means coupled tosaid peripheral request indicating means and said processor memoryaccess indicating means for permitting said peripheral unit to accesssaid memory independently of said processor when said processor is notaccessing the memory.
 87. In a computer system, a processor capable ofprocessing data in a plurality of cycles, said processor includingtiming means for initiating a processor cycle and for providing timingcontrol signals during each initiated processor cycle, said processoralso including a randomly accessible memory capable of being selectivelychosen for access by said processor in any one or more of said cycles,said processor including means operable in each cycle to provide aprocessor request signal indicating whether or not the processorrequires access to the memory during the next cycle, means includingprocessor address means and processor input-output means for cooperatingwith said memory to permit performance of a memory cycle during which aselected address in memory is accessed in accordance with said processoraddress means, said processor further including processor memory accessindicating means for indicating when the processor is using the memoryand processor memory request indicating means for indicating whether theprocessor requests access to the memory during the next processor cycle,at least one peripheral unit including peripheral address means andperipheral input-output means capable of cooperating with said memory inthe same manner as said processor address means and said processorinput-output means, the period of a cycle of said processor beingrelatively small with respect to the period between transfers of data bysaid peripheral unit, gating means for gating said address means andsaid input-output means so as to permit either the processor address andinput-output means or the peripheral address and input-output means toaccess said memory independently of one another, said peripheral unitalso including a peripheral request indicating means for indicating whensaid peripheral unit requests access to said memory, means coupled tosaid processor memory request indicating means and said peripheralrequest indicating means for inihibiting generation of a new processorcycle when both said processor and said peripheral unit request accessto the memory for the same period, and means coupled to said peripheralrequest indicating means and said processor memory access indicatingmeans for permitting said peripheral unit to access said memory via saidgating means when said processor is not accessing the memory.
 88. In acomputer system, a processor capable of processing data in a pluralityof cycles, said processor including a randomly accessible memory capableof being selectively chosen for access by said processor in any one ormore of said cycles, said processor including means operable in eachcycle to provide a processor request signal indicating whether or notthe processor requires access to the memory during the next cycle, meanscooperating with said memory to provide access thereto in discretememory cycles each of duration of the same order as a processor cycle,first indicating means for indicating when said processor is accessingsaid memory during a processor cycle, second processor indicating meansfor indicating when the next cycle of said processor requires access ofsaid memory, at least one peripheral unit including means for accessingsaid memory independently of said processor, said peripheral unit alsoincluding peripheral request indicating means, means coupled to saidfirst processor indicating means and said peripheral request indicatingmeans for permitting said peripheral to access said memory independentlyof said processor when said processor is not accessing the memory, theperiod of a cycle of said processor being relatively small with respectto the period between transfers of data by said peripheral unit, andmeans coupled to the first and second processor indicating means andsaid peripheral request indicating means for inhibiting the performanceof the next cycle by said processor when both said processor and saidperipheral unit request access to the memory for the same period, thenext processor cycle being inhibited until the peripheral unit completesa memory cycle.
 89. For use with a data processing system comprising, incombination, a computer, an addressable storage device storing data,channel instructions and further instructions including select andcontrol instructions, and a plurality of input/output devices, a controldevice comprising: channels coupling said input/output devices to saidaddressable storage device, means for interpreting said selectinstructions to render one channel operative to select a choseninput/output device, means interpreting said channel instructions toobtain a control instruction, means controlled by said controlinstruction for controlling the transfer of data via said selectedchannel, means controlled by said channel instruction for storing insaid selected channel the manifestation of the address of a next controlinstruction located in said storage means, and means rendered operativeupon completion of said transfer of data to render said manifestation ofthe address of a next control instruction effective to select and renderoperative said next control instruction.
 90. A control device as inclaim 89 including means for establishing priority of access to saidstorage device between said computer and said channels, and meanscontrolled by the selected channel operation to grant priority of accessto said channel instead of to said computer.
 91. A control device as inclaim 89 including means for establishing priority of access to saidstorage device, among said channels, means conditioned by operation of achosen channel, and means controlled by said conditioned means renderingsaid priority means operative to grant access to said chosen channel, inpreference to another channel.